Advanced packaging techniques as promising solutions to fulfill the needs of the semiconductor industry
The demand for constantly evolving semiconductor technologies remains high in the market, but Moore’s Law becomes increasingly difficult to achieve as node advancement reaches its limits, further scaling in advanced nodes being hardly cost-effective. As a result, the process of chip miniaturization has been slowing down and the semiconductor industry is facing a gap in technology advancement. Advanced packaging techniques, such as 2.5D, 3D, and fan-out wafer level packaging, have emerged as promising solutions to fill the gap and meet the needs of the semiconductor market. These new approaches allow for the integration of multiple dies into a single package, with the possibility of combining mature and advanced nodes.
The growth of the System-in-Package (SiP) market is driven by the 5G, artificial intelligence (AI), high-performance computing (HPC), autonomous driving, and Internet-of-Things (IoT) segments. While the semiconductor packaging market primarily uses flip-chip (FC) and wire-bond (WB) technologies, there is an increasing demand for integrating more components into a SiP in order to achieve smaller form factors and higher performance products.
There are competing interests between the cost increase per yielded mm2 of silicon leading-node technology and the insatiable demand for more compute and memory per package. The solution is more die connected with interconnect technologies. In order to address this issue, the semiconductor industry must employ more advanced interconnect technologies, such as Si interposers, embedded bridges, UHD RDLs, and others, as well as implement more vertical connections using TSVs, micro-bumps, Cu posts, bumpless Cu/SiO2 hybrid bonding, RDL vias, etc.
Challenges for packaging technologies
Three main advanced packaging technologies – wafer level packaging (WLP), 2.5D, and 3D stacking – have supplemented the dominant flip-chip and wire-bond technologies. The roadmap for these technologies is challenging and the supply chain is becoming increasingly competitive, with the demand for high-density fan-out (HD FO) redistribution layers (RDLs), high-density input/output interconnections (I/O) that require smaller line/space (L/S) patterns, and advanced 2.5D/3D packaging techniques such as silicon interposer and embedded bridge. Heterogeneous integration and chiplets are pushing for more complex system-in-package (SiP) solutions to be adopted. Chiplet-based approach offer smaller SiP footprints with lower power consumption and facilitate the integration of multiple dies using various interconnect methods such as high-density substrates, interposers, bridges, and hybrid bonding.
The market for 2.5/3D packaging is showing the most potential for growth. Currently, the highest revenue contributors are stacked CMOS image sensors (CIS) and silicon interposers. However, the technology with the most rapid growth is 3D SoC, driven by the trend of hybrid bonding for chiplets 3D integration. The partitioning of large dies into chiplets and heterogeneous integration are also important market trends that are driving the development of Fan-Out packaging. High density fan-out (HD FO) is currently the dominant market class, but the ultra-high density fan-out (UHD FO) is the highest-growing segment that will take market share from silicon interposers in the future with innovative FO-on-substrate and FO-embedded-bridge solutions.
Semiconductor packaging was primarily performed by outsourced semiconductor assembly and test companies (OSATs) such as ASE/SPIL, Amkor, JCET, etc. These companies continue to play an important role in this field, but it is TSMC, Samsung and Intel that have been offering advanced back-end solutions and using their front-end capabilities to develop innovative 2.5D/3D packaging solutions such as silicon interposer, embedded bridge, and hybrid bonding.
KnowMade’s purpose
KnowMade’s semiconductor packaging team offers a unique and valuable understanding of the latest innovations and ecosystem evolution in advanced packaging through patent analysis reports and monitoring services. Our analysts track and analyze the patent activity of leading companies, such as TSMC, Samsung, Intel, Amkor, ASE, SPIL, JCET, Nepes, PTI, Deca, Huatian, TFME, SJSemi, SK Hynix, Xperi, and others. We can provide insights into their technology roadmap and IP strategy, particularly in high-end performance packaging, including UHD Fan-Out, 2.5D silicon interposer or embedded bridge, 3D stacking of dies, and hybrid bonding.
Our packaging analysts pay special attention to the following technologies:
- Fan-Out packaging: fan-out wafer level packaging (e.g., Infineon’s eWLB, TSMC’s InFO, ASE’s FOCoS, etc.), fan-out panel level packaging (e.g., PTI’s CHIEFS, CLIP, PiFO, and BF2O, etc.), redistribution layers (RDL), chip-first / RDL-first, single-chip FO / multi-chip FO, FO-on-substrate, FO interconnect bridge, 3D multi-stack FO (stacked die, SoCs & memory integration), FO package-on-package (FO-PoP), FO antenna-in-package (FO AiP), etc.
- 2.5D packaging: silicon interposer (e.g., TSMC’s CoWoS-S, Intel’s Foveros, Samsung’s H-Cube and I-Cube), embedded silicon bridge (e.g., Intel’s EMIB and Co-EMIB, TSMC’s CoWoS-L and InFO_LSI, ASE’s FOCoS-Bridge), redistribution layers (e.g., TSMC’s CoWoS-R), glass interposer, etc.
- 3D packaging: 3D system-on-chip (3D SoC), 3D integrated circuit (3D IC), 3D stacked memory (e.g., HBM, 3D stacked DRAM, 3D NAND stack), TSV with µbumps/Cu pillars, bumpless hybrid bonding (e.g., Xperi’s DBI, TSMC’s SoIC, Intel’s Foveros Direct, YMTC’s Xtacking), 3D Fan-Out, 3D heterogeneous integration, chiplets, etc.
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